A flat disk or “wafer” of single crystal silicon is the basic substrate material in the semiconductor industry for the manufacture of integrated circuits. Semiconductor wafers are typically created by growing an elongated cylinder or boule of single crystal silicon and then slicing individual wafers from the cylinder. The slicing causes both faces of the wafer to be extremely rough. The front face of the wafer on which integrated circuitry is to be constructed must be extremely flat in order to facilitate reliable semiconductor junctions with subsequent layers of material applied to the wafer. Also, the material layers (deposited thin film layers usually made of metals for conductors or oxides for insulators) applied to the wafer while building interconnects for the integrated circuitry must also be made a uniform thickness.
Integrated circuits manufactured today are made up of literally millions of active devices such as transistors and capacitors formed in a semiconductor substrate. Integrated circuits rely upon an elaborate system of metalization in order to connect the active devices into functional circuits. A typical multilevel interconnect 100 is shown in FIG. 1. Active devices such as MOS transistors 107 are formed in and on a silicon substrate or well 102. An interlayer dielectric (ILD) 104, such as SiO2, is formed over silicon substrate 102. ILD 104 is used to electrically isolate a first level of metalization that is typically aluminum (Al), with copper (Cu) increasing in popularity, from the active devices formed in substrate 102. Metalized contacts 106 electrically couple active devices formed in substrate 102 to interconnections 108 of the first level of metalization. In a similar manner metal vias 112 electrically couple interconnections 114 of a second level of metalization to interconnections 108 of the first level of metalization. Contacts 106 and vias 112 typically comprise a metal 116 such as tungsten (W) surrounded by a barrier metal 118 such as titanium-nitride (TiN). Additional ILD/contact and metalization layers may be stacked one upon the other to achieve the desired interconnections. The ILD/contact and metalization layers may be formed, for example, using a dual damascene process.
Planarization is the process of removing projections and other imperfections to create a flat planar surface, both locally and globally, and/or the removal of material to create a uniform thickness for a deposited thin film layer on a wafer. Semiconductor wafers are planarized or polished to achieve a substantially smooth, flat finish before performing process steps that create the integrated circuitry or interconnects on the wafer. A considerable amount of effort in the manufacturing of modem complex, high density multilevel interconnects is devoted to the planarization of the individual layers of the interconnect structure. Nonplanar surfaces create poor optical resolution of subsequent photolithography processing steps. Poor optical resolution prohibits the printing of high-density lines. Another problem with nonplanar surface topography is the step coverage of subsequent metalization layers. If a step height is too large there is a serious danger that open circuits will be created. Planar surface layers are required in the fabrication of modem high-density integrated circuits. To this end, chemical-mechanical planarization (CMP) tools have been developed to provide controlled planarization of both structured and unstructured wafers.
CMP consists of a chemical process and a mechanical process acting together, for example, to reduce height variations across a dielectric region, clear metal deposits in damascene processes or remove excess oxide in shallow trench isolation fabrication. The chemical-mechanical process is achieved with a liquid medium containing chemicals that react with the front surface of the wafer when it is mechanically stressed during the planarization process.
In a conventional CMP tool for planarizing a wafer, a wafer is secured in a carrier connected to a shaft. The shaft is typically connected to mechanical means for transporting the wafer between a load or unload station and a position adjacent to a polishing pad mounted to a rigid or flexible platen or supporting surface. Pressure is exerted on the back surface of the wafer by the carrier in order to press the front surface of the wafer against the polishing pad, usually in the presence of slurry. The wafer and/or polishing pad are then moved in relation to each other via motor(s) connected to the shaft and/or,supporting surface in order to remove material in a planar manner from the front surface of the wafer.
It is often desirable to monitor the front surface of the wafer during the planarization process. One known method is to use an optical system that monitors the front surface of the wafer in situ by positioning an optical probe under the polishing pad. Laser interferometry, signal template matching and multifrequency analysis techniques, as well as others, are known monitoring methods. The signal from the probe may be transmitted and received through an opening in the polishing pad. The opening in the polishing pad may be filled with an optically transparent material, or “window”, in order to prevent polishing slurry or other contaminants from being deposited into the probe and obscuring the optical path to the wafer. The data from the optical system is typically analyzed by a control system to determine the current condition of the front surface of the wafer. It is possible to terminate the planarization process (call endpoint) once the front surface of the wafer has reached a desired condition. An optical system may be used to compensate for drifts in the planarization process, variability in the associated consumables (polishing pads and slurries), and variability in the thickness of incoming wafers.
A reliable end-point detection system is critical for maintaining an optimum CMP process. The end-point system detects the point in the planarization process when the overburden being polished is removed everywhere across the wafer. Excessive removal of overburden from the front surface of the wafer, whether a raw sheet film, or an STI, metal or dielectric layer structure on the front wafer surface, may damage the wafer. CMP of copper will become one of the most common and critical planarization processes when the copper interconnect technology starts to dominate the fabrication of integrated circuits. FIG. 2 illustrates some of the potential problems if excessive overburden is removed, in this case copper, from the front surface of a wafer. At time T1 a layer of deposited copper 200 remains on the wafer. The CMP planarization process should terminate at time T2 or just slightly thereafter for an optimum planarized surface. However, if the planarization process is not terminated quickly enough, excessive removal of copper in the interconnects 202 may occur as shown at time T3. The dishing of the copper interconnects 202 occurs since the copper is softer than the silicon dioxide 201 and is therefore removed at a faster rate.
End-point detection and monitoring is required for copper CMP due to the variations in the incoming thickness distribution of the copper film as well as microstructural variations in the deposited copper film. These result in nonuniform clearing of the copper across the front surface of the wafer. Several problems exist with conventional in situ monitoring techniques that limit their ability to accurately detect the clearing of the copper.
In addition, some conventional systems tend to measure a relatively large spot, or integrate a number of large spots (smear measurement), on the wafer's surface to increase the surface area of the wafer being monitored. However, these measurements create a system with very poor sensitivity that cannot distinguish high metalization density from mere residual metal. Improved sensitivity is required to detect residuals on the wafer's surface that are on the order of the spot size, but may influence the quality of the planarization process.
Applicants also noticed a further problem with some conventional monitoring systems in that they do not associate a measurement with the location on the wafer where the measurement was taken. This prevents in situ corrections to the planarization process based on information related to particular areas of the wafer.
Another problem Applicants noticed was that some conventional monitoring systems do not take measurements in fine enough increments along a radial line leaving concentric bands between measurements unmonitored. Problems in the planarization process typically manifest themselves as bands that are either being polished too quickly or too slowly. Conventional monitoring systems are not able to detect problem bands that lie totally within unmeasured bands (blind spots). This creates the very undesirable condition of having potential problem areas that are not detectable.
What is needed is a system for monitoring the front surface of a wafer during a planarization process that is able to take frequent measurements with one or more probes, has a small spot size for higher sensitivity in detecting small residuals, has the ability to associate a measurement with its location on the wafer, takes measurements at various points on the surface of the wafer in a time period critical to and relevant to the particular process, and can determine areas on the wafer that need an increased or decreased material removal rate.